1. Field of the Invention
The present invention relates to an image pickup device, wherein an output signal line is connected to each pixel array in an image pickup unit having pixels arranged in arrays, and a camera device including the image pickup device.
2. Description of the Related Art
As a typical image pickup device, wherein an output signal line is connected to each pixel array in an image pickup unit, for outputting a video signal generated by the pixels through the output signal line, a CMOS sensor is known (for example, refer to The Japanese Unexamined Patent Publication No. 2003-087662: the patent article 1).
FIG. 1 shows a pixel circuit of a CMOS sensor explained as the related art.
FIG. 1 shows a view of the configuration of outputting as a video signal charges (electrons) accumulated in a photodiode 100 to an output signal line 120. At this time, one side of the output signal line is connected to a sample hold circuit (S/H) and a correlation duplicate sample circuit (CDS) composing a column processing circuit, so that it has high impedance. Also, the other side of the output signal line 120 is connected to a current source 140 outside of the image pickup unit.
Each pixel of the CMOS sensor is provided with a photodiode (hereinafter, referred to as PD) 100 and four MOS transistors 200, 220, 240 and 260. Among them, the reset transistor 200 and a transfer transistor 220 are cascaded between a drive power source (power source voltage Vdd) and an output of the PD10, and a floating diffusion portion (hereinafter, referred to as an FD portion) 160 is provided between a source of the reset transistor 200 and a drain of the transfer transistor 220. Also, a selection transistor 240 and an amplifier transistor 260 are cascaded between the output signal line 120 and the power source voltage Vdd, and a gate of the amplifier transistor 260 is connected to the FD unit 160.
The reset transistor 200 is controlled by a set line 201, the selection transistor 240 is controlled by a selection line 241, and the transfer transistor 220 is controlled by a transistor line 221.
When reading a video signal, a reset pulse RDT is input to the gate of the reset transistor 200 via the set line 201, a transfer pulse TRS is input to the gate of the transfer transistor 220 via the transfer line 221, and a selection pulse SEL is input to the gate of the selection transistor 240 via the selection line 241.
In the above configuration, when the selection transistor 240 is turned on, the amplifier transistor 260 and a constant current source 140 outside of the image pickup unit form a source follower. Therefore, a voltage of the output signal line 120 becomes a value following to a gate voltage of the amplifier transistor 260, that is, a voltage of the FD portion 160. This value regulates an output of a pixel (a pixel signal level).
FIG. 2A to FIG. 2E are timing charts at reading a pixel signal.
Here, a transfer pulse TRS shown in FIG. 2A, a reset pulse RST shown in FIG. 2B, and a selection pulse SEL shown in FIG. 2C has a high level of a power source voltage Vdd and a low level of a reference voltage Vss (for example, a ground voltage). Therefore, transistors to be applied with the respective pulses turn on in a process that a voltage of the pulse applied to the gate reaches a level near the power source voltage Vdd. FIG. 2D and FIG. 2E show voltage changes of the FD portion 160 and output signal line 120 (refer to FIG. 1). In the figures, a value of a voltage itself between the power source voltage Vdd and the reference voltage Vss is determined at certain time even when the value changes over time. On the other hand, a voltage of the FD portion 160 before time T1 and after time T3 indicated as hatched portions in FIG. 2D is “uncertain” between the power source voltage Vdd and the reference voltage Vss.
Before reading a pixel signal, that is, before the time T1 shown in FIG. 2E, all of the four transistors 200, 220, 240 and 260 shown in FIG. 1 are turned off, and a voltage V0 of the output signal line 120 is held at the power source voltage Vdd.
When one pixel row is selected in this state, a selection line 241 corresponding to the pixel row (refer to FIG. 1) is applied with a selection pulse SEL shown in FIG. 2C. At the time T1 being approximately the same time as rising of the selection pulse SEL, a reset line 201 of the selected pixel row becomes active and a reset pulse RST rises as shown in FIG. 2B. Consequently, the reset transistor 200 shown in FIG. 1 turns on, and as shown in FIG. 2D, a voltage of the FD portion 160 having been uncertain until then becomes a high-level voltage (hereinafter, referred to as a reset voltage) V10, which is lower than the power source voltage Vdd exactly by a predetermined voltage, due to an effect by the reset transistor 200. Since the selection transistor 240 shown in FIG. 1 is already turned on, as shown in FIG. 2E, a voltage V0 of the output signal line 120 changes to a voltage V11, which is lower exactly by a differential voltage ΔV (hereinafter, referred to as a reset read voltage). Due to effects by the amplifier transistor 260 and the selection transistor 240 shown in FIG. 1, the reset read voltage V11 becomes a voltage between the power source voltage Vdd and the reference voltage Vss, which is normally furthermore lower than the above reset voltage V10. The differential voltage ΔV is a voltage determined comprehensively by the reset transistor 200, the amplifier transistor 260, a coupling capacitance thereof and the FD portion 160 and, furthermore, the selection transistor 240, etc.
When the transfer line 221 (refer to FIG. 1) becomes active, at the time T2 after a sufficient time for the reset read voltage V11 to become stabilized as shown in FIG. 2A, the transfer pulse TRS rises. Consequently, the reset transistor 200 shown in FIG.1 turns on, electrons accumulated in the photodiode 100 from a certain time after previous reading until then are transferred to the FD portion 160, and a potential of the FD portion 160 declines (a voltage V20). The decline of the potential is transferred to the output signal line 120 via the amplifier transistor 260 and the selection transistor 240 in turned on states. As a result, a voltage of the output signal line 120 furthermore declines from the reset read voltage V11 as shown in FIG. 2E exactly by an amount according to a charge amount (received light amount) of the electrons transferred to the FD portion 160 and becomes a voltage V21 (hereinafter, referred to as a pixel read voltage) in accordance with the received light amount of the photodiode 100.
Then, after the pixel read voltage V21 becomes stabilized, the application of the transfer pulse TRS finishes (FIG. 2A). When the selection pulse SEL falls at the T3 after a predetermined time after that, as shown in FIG. 2C, a voltage of the FD portion 160 again becomes “uncertain” as shown in FIG. 2D. After finishing the selection pulse SEL, a signal is output to outside of the sensor via the column processing circuit (not shown).
The above operation is repeated at predetermined cycles in units of each pixel row, and a video signal having level information in accordance with one picked-up image can be read from the successively output pixel signals.
As in the operation example explained above, a voltage of the output signal line changes to some levels when reading a pixel signal.
During a period, wherein a pixel row is selected and a selection pulse SEL is active, first, a reset read voltage (V11 in the example in FIG. 2E) appears in the output signal line 120. However, a voltage of the output signal line before that is the power source voltage Vdd, the reference voltage Vss or floating (the power source voltage Vdd in the example in FIG. 2E). The reset read voltage V11 is normally a voltage being lower than the power source voltage Vdd exactly by a differential voltage ΔV determined comprehensively by transistors in pixels and the production process as explained above but is higher than the reference voltage Vss.
Therefore, when shifting from the power source voltage Vdd or the reference voltage Vss to the set read voltage V11, it requires a certain time. When the initial state of the output signal line is floating, it may be a level close to the power source voltage Vdd or the reference voltage Vss, so that approximately the same time has to be estimated.
The time required for the voltage shift relates to a load on the output signal line 120 (a parasitic capacitance and resistance) and a drive ability of the amplifier transistor 260. Since the number of pixels in an image pickup device is increased recently, a load on the output signal line 120 is also increased thereby. Therefore, it takes time for a potential of the output signal line 120 to become stable and an interval between the time T1 and time T2 in FIG. 2 has to be long, which may result in a decline of the operation speed.
Also, when the initial state is floating, the initial voltage of the output signal line 120 depends on a pixel signal level at the time reading in the previous pixel row finishes (the time T3 in FIG. 2E). As a result, the initial voltage of the output signal line 120 fluctuates according to each pixel rows and columns, so that when an interval between the time T1 and time T2 is short, the fluctuation of the initial voltage easily becomes noise for the video signal.